1. Field of the Invention
The present invention relates to a semiconductor memory device including an SRAM cell.
2. Description of Related Art
There are semiconductor memory devices of a type which includes a memory cell where two PMOS transistors are connected to each other in series, one of the two PMOS transistors being used as a selection transistor including a selection gate whose voltage is controlled, and the other of the two PMOS transistors being used as a storage node including a floating gate whose voltage is not controlled (see Japanese Patent Application Laid-open Publications Nos. 2004-281971 and 2005-252267, for example). Writing to this type of memory cell is performed through drain avalanche hot electron injection into the floating gate in the storage node. The memory cells disclosed in Japanese Patent Application Laid-open Publications Nos. 2004-281971 and 2005-252267 have a configuration including a floating gate. Accordingly, a gate insulating film under the floating gate usually needs to be not smaller than 8 to 9 nm in thickness for the purpose of preventing the charges retention characteristic from deteriorating as a result that the floating gate loses electric charges. As the gate insulating film is thinner, deficiency increases in the insulating film serving as a pathway through which electrons accumulated in the floating gate are lost. This brings about a problem that the charges retention characteristic deteriorates extremely, and that the reliability accordingly decreases.
With this taken into consideration, disclosed are semiconductor memory devices of a type which includes no floating gate, and which performs write operations by changing the threshold voltage Vt in the MOS by use of the channel hot electron injection theory or the substrate hot electron injection theory (see Japanese Patent Application Laid-open Publications Nos. 2005-353106 and 2005-191506, for example). Vt shift usually does not take place so much in this case as any other transistor including a floating gate. For this reason, a configuration for an SRAM cell is adopted as a configuration for a memory cell included in a semiconductor memory device. This configuration makes it possible to sense a minute Vt change in the transistor.
Japanese Patent Application Laid-open Publication No. 2005-353106 (hereinafter referred to as “Patent Document 3”) discloses a semiconductor memory device in which two n-channel MISFETs (MNM1, MNM2) are connected to two storage nodes in a static semiconductor memory cell (SRAM) configured of 6 MIS transistors, and which includes a p-channel MISFET (MPEQ) connecting drains of the two n-channel MISFETs (MNM1, MNM2) (see FIG. 4). Gates of two transfer transistors T1 and T2 in the static semiconductor memory cell (SRAM) are connected to a single word line WL. A read operation of this memory cell is performed as follows. First, a threshold voltage Vt of one of the two n-channel MISFETs MNM1 and MNM2 is changed by use of the channel hot electron injection theory. Thus, the transfer transistors T1 and T2 are turned on. Thereby, the difference in electric current between the drains of the two respective n-channel MISFETs MNM1 and MNM2 is read to determine stored data.
Japanese Patent Application Laid-open Publication No. 2005-191506 (hereinafter referred to as “Patent Document 4”) discloses a vertical bipolar transistor which is configured of a source of a MOS transistor, a well, a substrate and a deep well, and in which electric charges (trap holes 473) are accumulated in a gate oxide film 465 and an oxide film side spacer 468 near the source so that Vt and Ion are changed (see FIG. 5). A method of injecting electric charges into the gate oxide film 465 and the oxide film side spacer 468 (a write operation) is performed as follows (see FIG. 7). For example, Vsub=0V is applied to a p-type silicon substrate 461; VN=−1V (VN<−Vbe: Vbe denotes a bias voltage) is applied to an n-type well 463 in order that the n-type well can be biased forwardly; and VS=0V is applied to a source 469. Thereby, hot holes 472 injected from the p-type silicon substrate 461 to the n-type well 463 are accelerated toward a vicinity of the source 469. By use of the substrate hot hole theory, trap holes 473 are injected into the gate oxide film 465 and the oxide film side spacer 468 near the source. The memory cell is configured as an SRAM using the operated PMOS as a load transistor (see FIG. 6).
In the case of Patent Document 3, in addition to the static semiconductor memory cell (SRAM), and the semiconductor memory device includes the n-channel MISFET (MNM1, MNM2) and the p-channel MISFET (MPEQ) for each memory cell. This brings about a problem that the transistors increase in number, and that the area of the memory cell accordingly increases.
In the case of Patent Document 4, a write operation needs the negative voltage (VN<−Vbe) for the purpose of accumulating charges (trap holes 473) in the gate oxide film 465 and the oxide film side spacer 468 near the source. This brings about a problem that the peripheral circuit is complicated. In addition, hot holes 472 have a higher barrier against the oxide film side spacer 468 than electrons. So that, the efficiency of injecting hot holes 472 into the oxide film side spacer 468 is actually low, and that Vt change occurring due to a write operation is small, and this brings about a problem that a write rate is low.
Patent Document 4 shows an example in which its disclosed technique is applied to a PMOS transistor. Nevertheless, its disclosed technique can be applied to an NMOS transistor in principle. A write operation can be performed on a deep n-type well as well as a gate oxide film and an oxide film side spacer of an NMOS transistor formed in a p-type well by use of the theory of substrate hot electron injection. In this case, however, the deep n-type well is necessary. For this reason, a step of forming a deep n-well needs to be added to a CMOS process which does not include a step of forming the deep n-well. This entails additional costs.